1. Field of the Invention
The present invention relates to a process for fabricating an integrated circuit. More specifically, the present invention relates to an integrated circuit fabrication process that improves transistor performance by avoiding excessive diffusion of dopants during annealing.
2. Description of the Related Art
Many integrated circuit fabrication processes are used to remove harmful defects and impurities from regions of a substrate wafer and to activate dopants diffused or implanted into the wafer. Thermal processing does more than simply repair implantation damage. For example, thermal processes are commonly used to generate several types of changes in material properties of a substrate wafer. Thermal processing is highly useful for electrically activating or exciting the implanted impurity atoms. Upon implantation most implanted impurities do not occupy substitutional sites in the substrate. Thermal processing moves the implanted impurities to the substitutional sites.
Accordingly, thermal processing, such as rapid thermal processing (RTP) or rapid thermal annealing (RTA), is used in multiple steps of a device fabrication process for silicon wafers. Rapid thermal annealing (RTA) involves short-time, high temperature processing to avoid unwanted dopant diffusion that would otherwise occur at the high processing temperatures of 900.degree. C. to 1000.degree. C. or greater that are used to dissolve extended defects in silicon (Si) and gallium arsenide (GaAs). The duration of an RTA process ranges from seconds to a few minutes so that semiconductor substrates are subjected to high temperatures only long enough to attain a desired process effect but not so long that a large degree of dopant diffusion takes place.
During the fabrication of integrated circuits, silicon wafers are processed to create precisely-controlled regions of dopants to activate conductive devices for usage in an integrated circuit. Thermal processing removes defects in silicon substrate resulting from processing steps having a destructive effect. One example of a processing step having a destructive effect is ion implantation, the introduction of selected impurity dopants into a substrate using high-voltage ion bombardment to modify electronic properties of the substrate.
Unfortunately, thermal treatments disadvantageously cause dopants to diffuse, reducing control of the concentration and location of the dopants. For devices having feature sizes in the range of 0.1-0.5 .mu.m or less, horizontal and vertical dopant diffusion must be reduced to maintain shallow junctions and controlled gate lengths. Two techniques have conventionally been used to minimize dopant diffusion including (1) low-temperature processing such as high-pressure oxidation and low-temperature CVD glass reflow, and (2) short-duration, high-temperature processing.
The temperature and the time duration of thermal processing are important processing parameters for determining functionality of fabricated integrated circuits. Suitable thermal processing involves application of thermal energy for a sufficient time and temperature to activate but not overly diffuse the dopants or impurities. A problem with thermal processing is that different dopants have different activation characteristics and diffusivities. The problem is magnified for rapid thermal processing because diffusivity differences between unlike dopants are amplified at high annealing temperatures. As a result, one dopant specifies may be insufficiently activated while a second dopant species is overannealed and diffused outside an intended channel so that control of transistor parameters is lost.
For example, semiconductor devices are typically fabricated by implanting boron as a P-type dopant and by implanting arsenic as an N-type dopant. After the dopants are implanted, the wafer upon which the semiconductor devices are formed is thermally annealed at a selected temperature and duration.
Under a particular set of rapid thermal processing conditions, a thermal processing step that is sufficient to activate the boron implant completely (100%) and to begin diffusing the boron outside the intended boundary for the P.sup.+ region is only activates an arsenic implant partially (for example, 60%). As a result, the thermal processing produces imperfect semiconductor devices having distributed ion implant damage sites that are not electrically active. As a result, the resistivity of the semiconductor is increased both by interspersed implanted atoms that are not activated and by damage sites in the silicon lattice caused by the implant bombardment. The partially-activated arsenic implant having a significant percentage of the dopant in the N.sup.+ region of a device without activation, results in a high N.sup.+ sheet resistance and a high potential for charge traps.
If the thermal processing parameters are modified to fully activate the arsenic implant, for example by increasing the temperature of annealing, the boron implant becomes highly over-diffused since the diffusivity of boron is fast and is a strong, nearly exponential, function of temperature.
The different diffusivities of boron and arsenic particularly cause problems in integrated circuits that combine P MOSFETs and N MOSFETs on the same wafer. Conventional processing includes a step of implanting lightly-doped drain (LDD) and heavily doped source drain implants of both boron for P-type implants and arsenic for N-type implants early in the process cycle. Multiple annealing processes typically are performed subsequent to the doping steps. The annealing processes cause the boron in the P-type implants to diffuse much more rapidly than the diffusion of arsenic in the N-type implants, substantially depleting the boron in the doped regions.
For example, a typical process flow includes the steps of forming gate electrodes in the N MOSFET and the P MOSFET regions, implanting the N.sup.- -type LDD implant and the P.sup.- -type LDD implant with intervening photoresist stripping steps, and forming sidewall spacers on the gate electrodes. The process flow proceeds with steps of implanting a heavily doped N.sup.+ -type source drain implant in the N MOSFETs, followed by stripping of photoresist protecting the P MOSFET region. The P MOSFETs are then doped by implanting the P.sup.- -type LDD implant and the heavily doped P.sup.+ -type source drain implant. Several rapid thermal annealing (RTA) steps are performed during this process to activate the transistors.
A problem arises because the boron P.sup.- LDD implant is very early in the process and boron diffuses very rapidly while the arsenic N-type implants diffuse slowly. For a sufficient annealing of the arsenic N-type implants, the boron P-type implants are diffused to the level of depletion. The boron implants cannot survive the heat of annealing.
What is needed is a technique for fabricating an integrated circuit including implanting and annealing multiple species of dopants having different diffusivities.